上課摘要：
■ 真值表程式
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity bol_vhdl is
port ( A,B,C: in STD_LOGIC;
D : out STD_LOGIC);
end bol_vhdl;
architecture a of bol_vhdl is
begin
D <= ((not A) and B and (not C))
or (A and B and (not C));
end a;
布林函數：
D ＝ A’BC’ + ABC’
■ 4對1多工器
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY MUX2_4 IS
PORT (S1,S0,d0,d1,d2,d3 : IN STD_LOGIC;
Y : OUT STD_LOGIC );
END MUX2_4;
ARCHITECTURE a OF MUX2_4 IS
BEGIN
Y <= ((not S1)and (not S0)and d0)
or((not S1)and S0 and d1)
or (S1 and (not S0)and d2)
or (S1 and S0 and d3);
END a;
■ 一對四的解多工器
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY demux1_4b IS
PORT (data : IN STD_LOGIC;
S1,S0 : IN STD_LOGIC;
D0,D1,D2,D3: OUT STD_LOGIC);
END demux1_4b ;
ARCHITECTURE a OF demux1_4b IS
BEGIN
D0<=data and (not S1)and (not S0);
D1<=data and (not S1)and S0;
D2<=data and S1 and (not S0);
D3<=data and S1 and S0;
END a;
作業指定：
- 請設計3對8解碼器，輸入變數分別為A, B, C, 輸出變數為Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7，專案名稱使用『d學號』。
